CMP is often used in the fabrication of integrated circuits to planarize a surface of a wafer to facilitate subsequent photolithographic process steps or to globally remove portions of a layer formed on the wafer. In particular, CMP can be used in fabricating inter-layer interconnects (e.g., metal plugs for contacts or vias), or for forming intra-layer interconnects (e.g., copper interconnect lines in a damascene process). In addition, CMP can be used in dual damascene processes in which both inter-layer and intra-layer interconnects are formed using deposition of a single metal layer.
FIG. 1 is a diagram illustrative of a conventional CMP system 10 for polishing a wafer 11. CMP system 10 includes a wafer carrier WC1 to hold wafer 11, a platen P1 with a polishing pad 13, and a slurry dispenser 15 with slurry S1. In conventional CMP system 10, a down force is applied to wafer carrier WC1 to achieve a polish pressure of F.sub.D1. To polish the surface of wafer 11, wafer carrier WC1 is also rotated at a rate of .omega..sub.WC1, while platen P1 is typically rotated in the opposite direction at a rate of .omega..sub.P1. In this example, dispenser 15 dispenses slurry S1 to the surface of polish pad 13 to facilitate the polishing process. In this example, slurry S1 is a slurry designed for metal polishing. A metal slurry (i.e., a slurry for metal polishing) is typically water-based, having abrasive particles on the order of twenty to two hundred nanometers in diameter in colloidal suspension. The slurry density is about 1% to 5% by weight, with a pH typically ranging from 3 to 11.
FIGS. 2A and 2B are diagrams illustrative of a cross-section of wafer 11 (FIG. 1) during a conventional single-step CWP process. To facilitate understanding of this description, the same reference numbers are used in several of the drawings to indicate elements having the same or similar function or structure. Referring to FIG. 2A, wafer 11 (FIG. 1) has a semiconductor substrate 21 with built in active device such as a transistor gate, upon which a dielectric layer 23, a barrier layer 25 and a metal layer 27 are formed. It will be appreciated that barrier layer 25 can also serve as an adhesion or glue layer for metal layers that do not readily adhere to dielectric layer 23. For example, metal layer 27 can be a Tungsten (W) layer, with CMP system 10 (FIG. 1) being used to remove the top portion of metal layer 27 to form W plugs in the contact holes in dielectric layer 23. Barrier layer 25 would typically be formed from Titanium (Ti), Titanium Nitride (TiN) or a Ti/TiN stack for barrier and adhesion purposes. FIG. 2B shows the resulting structure after the conventional CMP process is performed.
More specifically, referring to FIGS. 1, 2A and 2B, wafer 11 is held in wafer carrier WC1, with metal layer 27 facing polishing pad 13. Dispenser 15 dispenses metal slurry S1 onto the polishing pad 13 at a flow rate of FR1. Slurry S1 is typically chosen to more selective with respect to metal layer 27 relative to barrier layer 25 and dielectric layer 21. Platen P1 and wafer carrier WC1 are rotated at rates .omega..sub.P1, and .omega..sub.WC1, respectively. In addition, a down force F.sub.D1 is applied to wafer carrier WC1 to perform this conventional metal polishing process.
In this conventional process, dielectric layer 23 is used as an polish stopping layer for the CMP process. The polishing may continue for a relatively short period after the endpoint is detected to ensure that all of barrier layer 25 is cleared from the surface of dielectric layer 23. Because of the relatively high selectivity of slurry S1 for metal layer 27, the removal rate of metal layer 27 is greater than the removal rates for barrier layer 25 and dielectric layer 23. As a result, at the end of barrier layer removal, a relatively large amount of metal recess (or dishing) occurs in the contact holes, as indicated by metal layer 27, in FIG. 2A being below the level of the surrounding dielectric region. The amount of metal recess is indicated in FIG. 2B as .delta. In addition, dielectric layer 23 is removed at a faster rate near the contact holes relative to the field regions. It is believed that the contact holes may cause this difference in removal rate by weakening the structural integrity of dielectric layer 23 in the region of the contact holes. This effect is referred to herein as dielectric erosion. The amount of dielectric erosion is indicated in FIG. 2B as a. It will be appreciated that in a typical CMP application, it is desirable to minimize both .alpha. and .delta. while maximizing the throughput of wafers being processed by CMP system 10.
Another problem encountered in CMP is illustrated in FIG. 3. FIG. 3 shows a portion of dielectric layer 23 having microscratches 31 formed thereon, after being polished using metal slurry S1. Typically, a slurry that is effective in removing metal and barrier layers also causes microscratching of dielectric layers. Microscratching is generally undesirable in metal polishing because in severe cases, microscratching may result in short-circuiting of metal interconnects subsequently formed on the dielectric layer.
One conventional approach to solving the above dishing problem is illustrated in FIG. 4. FIG. 4 illustrates a two-platen two-slurry CMP system 40. CMP system 40 includes CMP subsystems 41 and 42. In this example, CMP subsystem 41 is implemented with CMP system 10 (FIG. 1), and CMP subsystem 42 is essentially a duplicate of CMP subsystem 41. In particular, CMP subsystem 42 includes a wafer carrier WC2, a platen P2 with a polishing pad 43, and a slurry dispenser 45 with slurry S2. A down force is applied to wafer carrier WC2 to achieve a polish pressure of F.sub.D2. Wafer carrier WC2 is rotated at a rate of .omega..sub.WC2, while platen P2 is rotated in the opposite direction at a rate of .omega..sub.P2. Dispenser 45 dispenses slurry S2 onto polishing pad 43 during this second polishing process. Subsystems 41 and 42 may be stations on a multi-station CMP machine, or separate CMP machines.
In this conventional approach, CMP subsystem 41 is used for metal polishing of wafer 11 using slurry S1, wafer carrier WC1 and platen P1, as described above for CMP system 10. Then, wafer 11 is cleaned (not shown) and transported to CMP subsystem 42 for dielectric polishing using a slurry S2. To reduce microscratching and/or dielectric erosion, slurry S2 is optimized for polishing dielectric layer 23 (i.e., sometimes referred to as "second platen buffing"). To reduce dishing, the metal layer polishing is performed using barrier layer 25 (FIG. 2A) as the metal polish endpoint. Wafer 11 is then transported to CMP subsystem 42 for barrier layer polishing using slurry S2, which is optimized for barrier layer polishing. These conventional systems use two platens because slurries S1 and S2 are typically incompatible. For example, metal slurries typically have a low pH while dielectric slurries have a high pH. Mixing these slurries on the same platen generally causes the abrasive particles in the slurries to flocculate and fall out of suspension, which undesirably reduces uniformity of the metal removal. However, the need for transporting the wafer to a second platen undesirably reduces throughput of CMP system 40. Therefore, there is a need for a CMP system that reduces dishing, dielectric erosion and microscratching without reducing wafer uniformity and throughput.